John L.Hennessy，斯坦福大學(xué)校長，IEEE和ACM會士，美國國家工程研究院院士及美國科學(xué)藝術(shù)研究院院士。Hennessy教授因為在RISC技術(shù)方面做出了突出貢獻(xiàn)而榮獲2001年的Eckert-Mauchly獎?wù)?，他也?001年Seymour Cray計算機(jī)工程獎得主，并且和本書另外一位作者David A. Patterson分享了2000年John von Neumann獎。David A. Patterson 加州大學(xué)伯克利分校計算機(jī)科學(xué)系主任、教授，美國國家工程研究院院士，IEEE和ACM會士，曾因成功的啟發(fā)式教育方法被IEEE授予James H. Mulligan，Jr.教育獎?wù)?。他因為對RISC技術(shù)的貢獻(xiàn)而榮獲1995年IEEE技術(shù)成就獎，而在RAID技術(shù)方面的成就為他贏得了1999年IEEE Reynold Johnson4R息存儲獎。2000年他John L. Hennessy分享了John yon Neumann獎。
圖書目錄
Foreword Preface Acknowledgments Chapter 1 Fundamentals of Quantitative Design and Analysis 1.1 Introduction 1.2 Classes of Computers 1.3 Defining Computer Architecture 1.4 Trends in Technology 1.5 Trends in Power and Energy in Integrated Circuits 1.6 Trends in Cost 1.7 Dependability 1.8 Measuring, Reporting, and Summarizing Performance 1.9 Quantitative Principles of Computer Design 1.10 Putting It All Together: Performance, Price, and Power 1.11 Fallacies and Pitfalls 1.12 Concluding Remarks 1.13 Historical Perspectives and References Case Studies and Exercises by Diana Franklin Chapter 2 Memory Hierarchy Design 2.1 Introduction 2.2 Ten Advanced Optimizations of Cache Performance 2.3 Memory Technology and Optimizations 2.4 Protection: Virtual Memory and Virtual Machines 2.5 Crosscutting Issues: The Design of Memory Hierarchies 2.6 Putting It All Together: Memory Hierachies in the ARM Cortex-AS and Intel Core i7 2.7 Fallacies and Pitfalls 2.8 Concluding Remarks: Looking Ahead 2.9 Historical Perspective and References Case Studies and Exercises by Norman P. Jouppi, Naveen Muralimanohar, and Sheng Li Chapter 3 nstruction-Level Parallelism and Its Exploitation 3.1 Instruction-Level Parallelism: Concepts and Challenges 3.2 Basic Compiler Techniques for Exposing ILP 3.3 Reducing Branch Costs with Advanced Branch Prediction 3.4 Overcoming Data Hazards with Dynamic Scheduling 3.5 Dynamic Scheduling: Examples and the Algorithm 3.6 Hardware-Based Speculation 3.7 Exploiting ILP Using Multiple Issue and Static Scheduling 3.8 Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and Speculation 3.9 Advanced Techniques for Instruction Delivery and Speculation 3.10 Studies of the Limitations oflLP 3.11 Cross-Cutting Issues: ILP Approaches and the Memory System 3.12 Multithreading: Exploiting Thread-Level Parallelism to Improve Uniprocessor Throughput 3.13 Putting It All Together: The Intel Core i7 and ARM Cortex-AS 3.14 Fallacies and Pitfalls 3.15 Concluding Remarks: What's Ahead? 3.16 Historical Perspective and References Case Studies and Exercises by Jason D. Bakos and Robert R Colwell Chapter4 Data-Level Parallelism in Vector, SIMD, and GPU Architectures 4.1 Introduction 4.2 Vector Architecture 4.3 SIMD Instruction Set Extensions for Multimedia 4.4 Graphics Processing Units 4.5 Detecting and Enhancing Loop-Level Parallelism 4.6 Crosscutting Issues 4.7 Putting It All Together: Mobile versus Server GPUS and Tesla versus Core i7 4.8 Fallacies and Pitfalls 4.9 Concluding Remarks 4.10 Historical Perspective and References Case Study and Exercises by Jason D. Bakos Chapter 5 Thread-Level Parallelism 5.1 Introduction 5.2 Centralized Shared-Memory Architectures 5.3 Performance of Symmetric Shared-Memory Multiprocessors …… Chapter6 Warehouse-Scale Computers to Exploit Request-Level and Data-Level Parallelism Appendix A Instruction Set Principles Appendix B Review of Memory Hierarchy Appendix C Pipelining: Basic and Intermediate Concepts
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