數(shù)字邏輯概論（英文版）

定　價：￥69.00

作　者：	陳娟,文泉主編
出版社：	北京大學出版社
叢編項：
標　簽：	暫缺

ISBN：	9787301343692	出版時間：	2023-09-01	包裝：
開本：		頁數(shù)：		字數(shù)：

內(nèi)容簡介

　　數(shù)字邏輯是計算機專業(yè)的必修課程，本教材采用英文編寫，以邏輯代數(shù)的函數(shù)方法為基礎，通過大量實踐案例和集成電路芯片的應用，系統(tǒng)介紹了數(shù)字邏輯的基本理論、數(shù)字電路的分析和設計方法。本教材共八章，內(nèi)容包含Number Systems and Codes、Logical Algebra、Digital Circuit、Combinational Logic Circuit、Flip-flop、Synchronous Sequential Logic Circuit、Verilog Implementation of Logic Circuit以及Memory and Programmable Logic Device。其中，Verilog Implementation of Logic Circuit與計算機學科后續(xù)課程（如計算機組成原理、計算機體系結構、微機接口技術等）銜接緊密，能幫助學生準備先導知識。本教材配套資源成熟，配有慕課視頻、PPT和授課大綱等數(shù)字化資源。本教材可作為高等學校計算機專業(yè)大類的本科生、留學本科生的數(shù)字邏輯課程教材，也可供從事數(shù)字電路研究與應用的科技工作者學習參考。

作者簡介

　　陳娟：：：：：：：陳娟，電子科技大學計算機科學與工程學院副教授，2009年獲英國布拉德福德大學計算機方向博士學位，長期講授本科生的中文和留學本科生的全英文“數(shù)字邏輯”課程。發(fā)表科研論文和教研論文30余篇。主持中央高?；究蒲袠I(yè)務費項目2項，主持校級教改項目7項，主辦國家自然科學基金國際合作項目1項，主研產(chǎn)學協(xié)同育人項目2項。文泉：：：：：：：電子科技大學計算機科學與工程學院，副教授。美國德克薩斯大學阿靈頓分校計算機科學與工程博士，美國伯克利國家實驗室博士后，已發(fā)表SCI/EI檢索論文50余篇，以第一負責人身份主持國家自然科學基金資助項目1項，接待國家自然科學基金外國青年學者研究基金1項。

圖書目錄

Chapter One Number Systems and Codes
1.1 Number Systems
1.2 Number Conversion
1.3 Signed Binary Numbers
1.4 Addition and Subtraction of Signed Binary Numbers
1.5 Numerical Codes
Exercise

Chapter Two Logical Algebra
2.1 Three Basic Functions of Logical Algebra
2.2 Laws and Rules of Logical Algebra
2.3 Compound Functions of Logical Algebra
2.4 Positive Logic and Negative Logic
2.5 Forms and Transformation of Logic Function
2.6 Simplification of Logic Function by Formula
2.7 Simplification of Logic Function by Kmap
Exercise

Chapter Three Digital Circuit
3.1 CMOS Transistor
3.2 Basic Logic Gates Implemented by CMOS Transistor
3.3 Other Types of Logic Gates in Digital Circuit
3.4 Unused Input of CMOS Circuit
3.5 Electrical Characteristics
3.6 TTL Transistor
3.7 Interface Compatibility of CMOS and TTL Transistors
Exercise

Chapter Four Combinational Logic Circuit
4.1 Analysis of Combinational Logic Circuit
4.2 Design of Combinational Logic Circuit
4.3 Universal Logic Gates
4.4 Arithmetic Circuits
4.5 Code Converter
4.6 Numerical Comparator
4.7 Encoder
4.8 Decoder
4.9 4 to 1 Line Data Selector (Multiplexer)
4.10 Hazard of Combinational Logic Circuit
Exercise

Chapter Five Flip flop
5.1 Definition of Flip flop
5.2 RS Flip flop
5.3 D Flip flop
5.4 JK Flip flop
5.5 Integrated Flip flop
5.6 The Other Types of Flip flop
5.7 Conversion Between Different Types of Flip flops
Exercise

Chapter Six Synchronous Sequential Logic Circuit
6.1 Definition of Synchronous Sequential Logic Circuit
6.2 Analysis of Synchronous Sequential Logic Circuit
6.3 State Simplification
6.4 Counter
6.5 Register
6.6 ShiftRegister Counter
6.7 Sequence Generator
6.8 Sequence Detector
6.9 Code Detector
Exercise

Chapter Seven Verilog Implementation of Logic Circuit
7.1 Basic Programming Grammar of Verilog
7.2 Verilog Implementation of the Logic Gates
7.3 Verilog Implementation of the Combinational Logic Circuit
7.4 Verilog Implementation of the Flip flop
7.5 Verilog Implementation of the Synchronous Sequential Logic Circuit
Exercise

Chapter Eight Memory and Programmable Logic Device
8.1 PLD
8.2 ROM
8.3 RAM
Exercise

Bibliography